(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices and more specifically to a method used to achieve the desired capacitance for DRAM devices using trench capacitor structures featuring narrow diameters.
(2) Description of Prior Art
The advent of micro-miniaturization, or the ability to fabricate semiconductor devices with sub-micron features, has allowed device performance to be increased, while decreasing fabrication costs. Smaller device features allow performance degrading junction capacitances to be reduced, while a greater number of smaller semiconductor chips can now be obtained from a specific size starting substrate, thus reducing the fabrication cost for a specific semiconductor chip. One area in which micro-miniaturization has presented difficulties is with the use of trench capacitor structures, for dynamic random access memory (DRAM), devices. To supply the desired signal the capacitance of the DRAM trench capacitor has to be maximized. To continually satisfy designs demanding increased capacitance, the depth of the trench shape has to be increased. In addition to satisfy device or cell density, the trench shape is designed with diameters as narrow as 0.10 um. The combination of deep trenches and narrow diameters result in difficulties when attempting to define this combination using dry etching and post-clean procedures. Anisotropic reactive ion etching (RIE), procedures can be limited when defining a narrow diameter trench shape, at depths greater than about 6 to 10 um. The reactants and by-products of the RIE procedure can be difficult to remove from the large aspect ratio opening, thus interfering with the ability to define a deep, narrow diameter trench shape. In addition post-clean procedures may be not be able to completely remove the by-products and contaminants from the large aspect ratio trench shape opening, thus presenting difficulties when forming a capacitor dielectric layer on the exposed surface of the trench opening. The capacitor dielectric, or node layer, can be formed with inadequate dielectric characteristics, in the large aspect ratio trench opening, resulting in yield loss or reliability problems for the trench capacitor DRAM device.
This invention will describe a process in which the desired capacitance values, using trench capacitors, can be obtained for DRAM designs, however without the process difficulties presented wit deep, narrow diameter openings. This is accomplished via a novel process sequence using silicon on insulator (SOI), bonding procedures, in which a deep, wide diameter trench capacitor structure is formed in an underlying semiconductor substrate, while an overlying semiconductor substrate, featuring a connecting narrow trench shape, is bonded to the underlying semiconductor structure, allowing communication to the deep, wide diameter capacitor structure to be realized. This configuration allows sub-micron features to be employed for the DRAM trench shape and transfer gate transistor, in a portion of the overlying bonded wafer, while the capacitance requirement is satisfied using the deep, wide diameter trench shape, located in the underlying semiconductor substrate. Prior art, such as Mandelman et al, in U.S. Pat. No. 6,163,045, describe the fabrication of a DRAM device featuring a trench capacitor structure, however that prior art does not describe the novel process sequence supplied in this present invention in which the trench capacitance is satisfied via formation of a deep, wide diameter trench capacitor structure in an underlying semiconductor substrate while an overlying SOI type bonded wafer is used to accommodate a connecting, shallow, narrow diameter trench shape, as well as to accommodate the transfer gate transistor.
It is an object of this invention to fabricate a DRAM cell, featuring trench capacitor structures.
It is another object of this invention to form deep, wide diameter trench capacitor structures in an underlying semiconductor substrate.
It is still another object of this invention to form narrow diameter trench shapes in an overlying semiconductor substrate, bonded to an underlying semiconductor substrate, via silicon on insulator (SOI), procedures, and with the narrow diameter trench shape overlying and contacting the underlying, deep, wide diameter trench capacitor structures located in the underlying semiconductor substrate.
In accordance with the present invention a method of forming a DRAM cell in which the capacitance of a DRAM device is increased by forming a deep, wide diameter trench capacitor structure in an underlying semiconductor substrate, contacted by an overlying narrow diameter, polysilicon filled trench shape, located in an overlying semiconductor substrate, bonded to the underlying semiconductor substrate via SOI procedures, is described. Deep, wide diameter trench shapes are formed in a first semiconductor substrate, followed by formation of a buried plate region, surrounding the deep, wide diameter trench shapes. After forming a dielectric node layer on the surfaces of the deep, wide diameter trench shapes, deposition of in situ doped polysilicon followed by a chemical mechanical procedure, are used to form deep, wide diameter trench capacitor structures in the first semiconductor substrate. A second semiconductor substrate is then subjected to a splitting ion implantation procedure, then bonded to the underlying first semiconductor substrate via SOI bonding procedures. After polishing back the top portion of the second semiconductor substrate to a level in which the splitting ion implanted region is exposed, dielectric layers are deposited followed by the definition of narrow diameter trench shapes, in the dielectric layer and in the thinned, second semiconductor substrate, exposing a portion of the top surface of the deep, wide diameter capacitor trench structures. Formation of a collar layer on the sides of the narrow diameter trench shapes is followed by deposition of, and recessing of, an in situ doped polysilicon layer. After removal of exposed portions of the collar layer, another in situ doped polysilicon layer is deposited, resulting in a narrow diameter trench structure, located in the thinned, second semiconductor substrate, overlying and contacting a portion of the top surface of the deep, wide diameter capacitor trench structure, located in the underlying, first semiconductor substrate. Formation of transfer gate transistor elements, word line and bit line structures complete the fabrication of a DRAM cell, employing high capacitance trench structures located in an underlying semiconductor substrate, and employing contacting, narrow diameter trench structures, and transfer gate transistor elements, located in an overlying second semiconductor substrate.